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  W9464G6IB 1m 4 banks 16 bits ddr sdram publication release date:oct. 16, 2008 - 1 - revision a01 table of contents- 1. general des cription ......................................................................................................... 4 2. features ....................................................................................................................... .......... 4 3. key parameters ................................................................................................................. .. 5 4. ball config uration ............................................................................................................ 6 5. ball descri ption............................................................................................................... ... 7 6. block diagram .................................................................................................................. .... 8 7. functional d escription.................................................................................................... 9 7.1 power up sequence....................................................................................................... 9 7.2 command fu ncti on ...................................................................................................... 10 7.2.1 bank activa te command ........................................................................................ 10 7.2.2 bank precha rge co mmand .................................................................................... 10 7.2.3 precharge a ll comma nd ........................................................................................ 10 7.2.4 write co mmand...................................................................................................... 10 7.2.5 write with auto-p recharge command..................................................................... 10 7.2.6 read co mmand ..................................................................................................... 10 7.2.7 read with auto-p recharge command .................................................................... 10 7.2.8 mode register set command ................................................................................ 11 7.2.9 extended mode regi ster set command ................................................................ 11 7.2.10 no-operati on comma nd ........................................................................................ 11 7.2.11 burst read st op command.................................................................................... 11 7.2.12 device desele ct co mmand .................................................................................... 11 7.2.13 auto refres h comma nd ......................................................................................... 11 7.2.14 self refresh entry command ................................................................................. 12 7.2.15 self refresh exit command ................................................................................... 12 7.2.16 data write enable /disable comm and ................................................................... 12 7.3 read oper ation............................................................................................................. 12 7.4 write oper ation............................................................................................................. 13 7.5 precharge ..................................................................................................................... 13 7.6 burst term ination.......................................................................................................... 13 7.7 refresh op eration......................................................................................................... 13 7.8 power down mode ....................................................................................................... 14 7.9 input clock freq uency change during precha rge power do wn mode........................ 14 7.10 mode register operation.............................................................................................. 14 7.10.1 burst length field (a2 to a0)................................................................................... 14
W9464G6IB publication release date:oct. 16, 2008 - 2 - revision a01 7.10.2 addressing mode select (a3) ................................................................................. 15 7.10.3 cas latency field (a6 to a4) .................................................................................. 16 7.10.4 dll reset bit (a8) .................................................................................................. 16 7.10.5 mode register/ext ended mode register ch ange bits ( ba0, ba1) ........................... 16 7.10.6 extended mode r egister field................................................................................. 17 7.10.7 reserved field......................................................................................................... 17 8. operatio n mode ................................................................................................................. 18 8.1 simplified tr uth table................................................................................................... 18 8.2 function trut h tabl e..................................................................................................... 19 8.3 function truth t able for cke ....................................................................................... 22 8.4 simplified stat ed diagram ............................................................................................ 23 9. electrical cha racteristics......................................................................................... 24 9.1 absolute maxi mum ratings .......................................................................................... 24 9.2 recommended dc oper ating conditions .................................................................... 24 9.3 capacitance .................................................................................................................. 25 9.4 leakage and output buffe r characte ristics.................................................................. 25 9.5 dc characte ristics ........................................................................................................ 26 9.6 ac characteristics and operating condition................................................................ 27 9.7 ac test co nditions ....................................................................................................... 28 10. system characteristic s for ddr sdram................................................................. 30 10.1 table 1: input slew ra te for dq, dqs, and dm .......................................................... 30 10.2 table 2: input setup & hold time derating fo r slew rate ........................................... 30 10.3 table 3: input/output setup & hold time derating for slew rate ............................... 30 10.4 table 4: input/output setup & hold de rating for rise/fall delta slew rate................ 30 10.5 table 5: output slew rate ch aracteristics (x 16 device s only) ................................... 30 10.6 system notes:............................................................................................................... 31 11. timing wa veforms ............................................................................................................. 33 11.1 command input timing ................................................................................................ 33 11.2 timing of the clk signals ............................................................................................ 33 11.3 read timing (bur st length = 4) ................................................................................... 34 11.4 write timing (bur st length = 4).................................................................................... 35 11.5 dm, data mask (W9464G6IB) .................................................................................. 36 11.6 mode register se t (mrs) timing................................................................................. 37 11.7 extend mode register set (emrs) timing .................................................................. 38 11.8 auto-precharge timing (r ead cycle, cl = 2) .............................................................. 39 11.9 auto-precharge timing (read cycl e, cl = 2), continued ............................................. 40 11.10 auto-precharge timi ng (write cycle) .......................................................................... 41
W9464G6IB publication release date:oct. 16, 2008 - 3 - revision a01 11.11 read interrupted by read (c l = 2, bl = 2, 4, 8) ........................................................ 42 11.12 burst read st op (bl = 8) ............................................................................................ 42 11.13 read interrupted by write & bst (bl = 8).................................................................. 43 11.14 read interrupted by precharge (bl = 8) ..................................................................... 43 11.15 write interrupted by wri te (bl = 2, 4, 8) ..................................................................... 44 11.16 write interrupted by r ead (cl = 2, bl = 8) ................................................................ 44 11.17 write interrupted by r ead (cl = 3, bl = 4) ................................................................ 45 11.18 write interrupted by precharge (bl = 8) ..................................................................... 45 11.19 2 bank interleave read operation (cl = 2, bl = 2) ................................................... 46 11.20 2 bank interleave read operation (cl = 2, bl = 4) ................................................... 46 11.21 4 bank interleave read operation (cl = 2, bl = 2) ................................................... 47 11.22 4 bank interleave read operation (cl = 2, bl = 4) ................................................... 47 11.23 auto refres h cycle ..................................................................................................... 48 11.24 precharge/activate power down mode entry and exit timing ................................... 48 11.25 input clock frequen cy change during precharge power down mode timing .......... 48 11.26 self refresh entr y and exit timing ............................................................................. 49 12. package specif ication .................................................................................................... 50 12.1 60 ball tfbga (8x13mm)............................................................................................. 50 13. revision histor y ............................................................................................................... . 51
W9464G6IB publication release date:oct. 16, 2008 - 4 - revision a01 1. general description W9464G6IB is a cmos double data rate synchronous dyna mic random access memory (ddr sdram); organized as 1m words 4 banks 16 bits. W9464G6IB delivers a data bandwidth of up to 400m words per second (-5) compliant to the ddr400/cl3 specification. all inputs reference to the positive edge of clk (except for dq, dm and cke). the timing reference point for the differential clock is when the clk and clk signals cross during a transition. write and read data are synchronized with the both edges of dqs (data strobe). by having a programmable mode r egister, the system can change burst length, latency cycle, interleave or sequential burst to maximize it s performance. W9464G6IB is ideal for any high performance applications. 2. features ? 2.5v 0.2v power supply ? up to 200 mhz clock frequency ? double data rate architecture; two data transfers per clock cycle ? differential clock inputs (clk and clk ) ? dqs is edge-aligned with data for read; center-aligned with data for write ? cas latency: 2, 2.5 and 3 ? burst length: 2, 4 and 8 ? auto refresh and self refresh ? precharged power down and active power down ? write data mask ? write latency = 1 ? 15.6s refresh interval (4k/64 ms refresh) ? maximum burst refresh cycle: 8 ? interface: sstl_2 ? packaged in 60 ball tfbga, using lead free materials with rohs compliant
W9464G6IB publication release date:oct. 16, 2008 - 5 - revision a01 3. key parameters symbol description min./max. -5 min. 7.5 ns cl = 2 max. 10 ns min. 6 ns cl = 2.5 max. 10 ns min. 5 ns t ck clock cycle time cl = 3 max. 10 ns t ras active to precharge command period min. 40 ns t rc active to ref/active command period min. 55 ns i dd0 operating current: one bank active-precharge max. 120 ma i dd1 operating current: one bank active-read-precharge max. 140 ma i dd2f precharge floating standby current max. 50 ma i dd2q precharge quiet standby current max. 50 ma i dd4r burst operation read current max. 185 ma i dd4w burst operation write current max. 180 ma i dd5 auto refresh current max. 210 ma i dd6 self refresh current max. 2.5 ma
W9464G6IB publication release date:oct. 16, 2008 - 6 - revision a01 4. ball configuration a b c d e f g h j k l m vssq vddq dq14 dq12 dq10 dq8 vref dq15 vss vddq vssq vddq vssq vss clk nc a11 a8 a6 a4 dq13 dq11 dq9 udqs udm clk cke a9 a7 a5 vss dq1 dq3 dq5 dq7 nc dq0 vdd dq2 dq4 dq6 ldqs ldm we ras ba1 a0 a2 vdd a3 a1 a10/ap ba0 cs cas vdd vddq vssq vddq vssq 123 789 : ball existing : depopulated ball top view (see the balls through the package) 0.8 mm 8.0 mm 13.0 mm 1.0 mm 12 3 4 5 6 7 8 9 a b c d e f g h j k l m bga package ball pattern top view device ball pattern
W9464G6IB publication release date:oct. 16, 2008 - 7 - revision a01 5. ball description ball number symbol function description k7, l8, l7, m8, m2, l3, l2, k3, k2, j3, k8, j2 a0 ? a11 address multiplexed pins for row and column address. row address: a0 ? a11. column address: a0 ? a7. (a10 is used for auto-precharge) j8, j7 ba0, ba1 bank select select bank to activate during row address latch time, or bank to read/write during column address latch time. a8, b9, b7, c9, c7, d9, d7, e9, e1, d3, d1, c3, c1, b3, b1, a2 dq0 ? dq15 data input/ output the dq0 ? dq15 input and out put data are synchronized with both edges of dqs. e7, e3 ldqs, udqs data strobe dqs is bi-directional signal. dqs is input signal during write operation and output signal duri ng read operation. it is edge- aligned with read data, center-aligned with write data. h8 cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. h7, g8, g7 ras , cas , we command inputs command inputs (along with cs ) define the command being entered. f7, f3 ldm, udm write mask when dm is asserted ?high? in burst write, the input data is masked. dm is synchronized with both edges of dqs. g2, g3 clk, clk differential clock inputs all address and control input signals are sampled on the crossing of the positive edge of clk and negative edge of clk . h3 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. f1 v ref reference voltage v ref is reference voltage for inputs. f8, m7, a7 v dd power (+2.5v) power for logic circuit inside ddr sdram. a3, f2, m3 v ss ground ground for logic circuit inside ddr sdram. b2, d2, c8, e8, a9 v ddq power (+2.5v) for i/o buffer separated power from v dd , used for output buffer, to improve noise. a1, c2, e2, b8, d8 v ssq ground for i/o buffer separated ground from v ss , used for output buffer, to improve noise. h2, f9 nc no connection no connection
W9464G6IB publication release date:oct. 16, 2008 - 8 - revision a01 6. block diagram cke a10 dll clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 4096 * 256 * 16 row decoder row decoder row decoder row decoder a0 a9 a11 ba0 ba1 cs ras cas we clk clk dq0 dq15 prefetch register ldm udm udqs ldqs
W9464G6IB publication release date:oct. 16, 2008 - 9 - revision a01 7. functional description 7.1 power up sequence (1) apply power and attempt to cke at a low state ( 0.2v), all other inputs may be undefined 1) apply v dd before or at the same time as v ddq . 2) apply v ddq before or at the same time as v tt and v ref . (2) start clock and maintain stable condition for 200 s (min.). (3) after stable power and clock, apply nop and take cke high. (4) issue precharge command fo r all banks of the device. (5) issue emrs (extended mode register set) to enable dll and establish output driver type. (6) issue mrs (mode register set) to reset dll and set device to idle with bit a8. (an additional 200 cycles(min) of clock are required for dll lock before any executable command applied.) (7) issue precharge command fo r all banks of the device. (8) issue two or more auto refresh commands. (9) issue mrs-initialize device operation with the reset dll bit deactivated a8 to low. 2 clock min. t rfc mrs clk command any cmd aref aref prea mrs emrs prea clk t rfc t rp t rp enable dll dll reset with a8 = high disable dll reset with a8 = low 200 clock min. 2 clock min. 2 clock min. inputs maintain stable for 200 s min. initialization sequence after power-up
W9464G6IB publication release date:oct. 16, 2008 - 10 - revision a01 7.2 command function 7.2.1 bank activate command ( ras = ?l?, cas = ?h?, we = ?h?, ba0, ba1 = bank, a0 to a11 = row address) the bank activate command activates the bank designated by the ba (bank address) signal. row addresses are latched on a0 to a11 when this co mmand is issued and the cell data is read out of the sense amplifiers. the maximum time that each b ank can be held in the active state is specified as t ras (max) . after this command is issued, read or write operation can be executed. 7.2.2 bank precharge command ( ras = ?l?, cas = ?h?, we = ?l?, ba0, ba1 = bank, a10 = ?l ?, a0 to a9, a11 = don?t care) the bank precharge command percharges the bank designated by ba. the precharged bank is switched from the active state to the idle state. 7.2.3 precharge all command ( ras = ?l?, cas = ?h?, we = ?l?, ba0, ba1 = don?t care, a10 = ?h?, a0 to a9, a11 = don?t care) the precharge all command precharges all banks simultaneously. then all banks are switched to the idle state. 7.2.4 write command ( ras = ?h?, cas = ?l?, we = ?l?, ba0, ba1 = bank, a10 = ?l?, a0 to a7 = co lumn address) the write command performs a write operation to the bank designated by ba. the write data are latched at both edges of dqs. the length of the write data (burst length) and column access sequence (addressing mode) must be in the mode register at power- up prior to the write operation. 7.2.5 write with auto-precharge command ( ras = ?h?, cas = ?l?, we = ?l?, ba0, ba1 = bank, a10 = ?h?, a0 to a7 = co lumn address) the write with auto-precharge command performs the precharge operation automatically after the write operation. this command must not be interrupted by any other commands. 7.2.6 read command ( ras = ?h?, cas = ?l?, we = ?h?, ba0, ba1 = bank, a10 = ?l?, a0 to a7 = co lumn address) the read command performs a read operation to the bank designated by ba. the read data are synchronized with both edges of dqs. the length of read data (burst length), addressing mode and cas latency (access time from cas command in a clock cycle) must be programmed in the mode register at power-up prior to the read operation. 7.2.7 read with auto-precharge command ( ras = ?h?, cas = ?l?, we = ?h?, ba0, ba1 = bank, a10 = ?h?, a0 to a7 = column address) the read with auto-precharge command automatic ally performs the precharge operation after the read operation. 1. reada t ras (min) ? (bl/2) x t ck
W9464G6IB publication release date:oct. 16, 2008 - 11 - revision a01 internal precharge operation begins after bl/2 cycle from read with auto-precharge command. 2. t rcd(min) reada < t ras(min) ? (bl/2) x t ck data can be read with shortest latency, but the internal precharge operation does not begin until after t ras (min) has completed. this command must not be interrupted by any other command. 7.2.8 mode register set command ( ras = ?l?, cas = ?l?, we = ?l?, ba0 = ?l?, ba1 = ?l?, a0 to a11 = register data) the mode register set command programs the va lues of cas latency, addressing mode, burst length and dll reset in the mode register. the default values in the mode register after power- up are undefined, therefore this command must be issued during the power-up sequence. also, this command can be issued while all banks are in t he idle state. refer to the table for specific codes. 7.2.9 extended mode register set command ( ras = ?l?, cas = ?l?, we = ?l?, ba0 = ?h?, ba1 = ?l?, a0 to a11 = register data) the extended mode register set command can be implemented as needed for function extensions to the standard (sdr-sdram). current ly the only available mode in emrs is dll enable/disable, decoded by a0. the default value of the extended mode register is not defined; therefore this command must be issued during t he power-up sequence for enabling dll. refer to the table for specific codes. 7.2.10 no-operation command ( ras = ?h?, cas = ?h?, we = ?h?) the no-operation command simply performs no operation (same command as device deselect). 7.2.11 burst read stop command ( ras = ?h?, cas = ?h?, we = ?l?) the burst stop command is used to stop the burst operation. this command is only valid during a burst read operation. 7.2.12 device deselect command ( cs = ?h?) the device deselect command disables the command decoder so that the ras , cas , we and address inputs are ignored. this command is similar to the no-operation command. 7.2.13 auto refresh command ( ras = ?l?, cas = ?l?, we = ?h?, cke = ?h?, ba0, ba1, a0 to a11 = don?t care) auto refresh is used during normal operation of the ddr sdram and is analogous to cas? before?ras (cbr) refresh in previous dram ty pes. this command is non persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the ddr sdram requires auto re- fresh cycles at an average periodic interval of t refi (maximum).
W9464G6IB publication release date:oct. 16, 2008 - 12 - revision a01 to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a ma ximum of eight auto refresh commands can be posted to any given ddr sdram, and the maximum absolute interval between any auto refresh command and the next auto refresh command is 8 * t refi . 7.2.14 self refresh entry command ( ras = ?l?, cas = ?l?, we = ?h?, cke = ?l?, ba0, ba1, a0 to a11 = don?t care) the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the se lf refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). the dll is automatically disabled upon entering self refresh, and is automatically enabled upon exiting self refresh. any time the dll is enabled a dll reset must follow and 200 clock cycles should occur before a read command can be issued. input signals except cke are ?don?t care? during self refresh. since cke is an sstl_2 input, v ref must be maintained during self refresh. 7.2.15 self refresh exit command (cke = ?h?, cs = ?h? or cke = ?h?, ras = ?h?, cas = ?h?) the procedure for exiting self refresh require s a sequence of commands. first, clk must be stable prior to cke going back high. once cke is high, the ddr sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both re fresh and dll requirements is to apply nops for 200 clock cycles before applying any other command. the use of self refreh mode introduces the po ssibility that an interna lly timed event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recommended. 7.2.16 data write enable /disable command (dm = ?l/h? or ldm, udm = ?l/h?) during a write cycle, the dm or ldm, udm signal functions as data mask and can control every word of the input data. the ldm signal controls dq0 to dq7 and udm signal controls dq8 to dq15. 7.3 read operation issuing the bank activate command to the idle ban k puts it into the active state. when the read command is issued after t rcd from the bank activate command, the data is read out sequentially, synchronized with both edges of dqs (burst read operation). the initial read data becomes available after cas latency from the issuing of the read command. the cas latency must be set in the mode register at power-up. when the precharge operation is performed on a bank during a burst read and operation, the burst operation is terminated. when the read with auto-precharge command is issued, the precharge operation is performed automatically after the read cycle then the bank is switched to the idle state. this command cannot be interrupted by any other commands. refer to the diagrams for read operation.
W9464G6IB publication release date:oct. 16, 2008 - 13 - revision a01 7.4 write operation issuing the write command after t rcd from the bank activate command. the input data is latched sequentially, synchronizing with both edges(rising & falling) of dqs after the write command (burst write operation). the bur st length of the write data (b urst length) and addressing mode must be set in the mode register at power-up. when the precharge operation is performed in a bank during a burst write operation, the burst operation is terminated. when the write with auto-precharge command is issued, the precharge operation is performed automatically after the write cycle, then the bank is switched to the id le state, the write with auto- precharge command cannot be interrupted by any other command for the entire burst data duration. refer to the diagrams for write operation. 7.5 precharge there are two commands, which perform t he precharge operation (bank precharge and precharge all). when the bank precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. the bank precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. the maximum time each bank can be held in the active state is specified as t ras (max) . therefore, each bank must be precharged within t ras(max) from the bank activate command. the precharge all command can be used to prec harge all banks simultaneously. even if banks are not in the active state, the precharge all command can still be issued. in this case, the precharge operation is performed only for t he active bank and the precharge bank is then switched to the idle state. 7.6 burst termination when the precharge command is used for a bank in a burst cycle, the burst operation is terminated. when burst read cycle is interr upted by the precharge command, read operation is disabled after clock cycle of (cas latency) from the precharge command. when the burst write cycle is interrupted by the prechar ge command, the input circuit is re set at the same clock cycle at which the precharge command is issued. in this case, the dm signal must be asserted ?high? during t wr to prevent writing the invalided data to the cell array. when the burst read stop command is issued for the bank in a burst read cycle, the burst read operation is terminated. the burst read stop command is not supported during a write burst operation. refer to the diagrams for burst termination. 7.7 refresh operation two types of refresh operation can be performed on the device: auto refresh and self refresh. by repeating the auto refresh cycle, each bank in turn refreshed automatically. the refresh operation must be performed 4096 times (rows) within 64ms. the period between the auto refresh command and the next command is specified by t rfc . self refresh mode enters issuing the self refr esh command (cke asserted ?low?) while all banks are in the idle state. the device is in self refr esh mode for as long as cke held ?low?. in the case of distributed auto refresh commands, distribut ed auto refresh commands must be issued every 15.6 s and the last distributed auto refresh co mmands must be performed within 15.6 s before entering the self refresh mode. after exiting from the self refresh mode, the refresh operation must be performed within 15.6 s. in self refr esh mode, all input/output buffers are disabled,
W9464G6IB publication release date:oct. 16, 2008 - 14 - revision a01 resulting in lower power dissipation (except cke buffer). refer to the diagrams for refresh operation. 7.8 power down mode two types of power down mode can be performed on the device: active standby power down mode and precharge standby power down mode. when the device enters the power down mode, al l input/output buffers are disabled resulting in low power dissipation (except cke buffer). power down mode enter asserting cke ?low? while the device is not running a burst cycle. taking cke ?high? can exit this mode. when cke goes high, a no operation command must be input at next clk rising edge. refer to the diagrams for power down mode. 7.9 input clock frequency change during precharge power down mode ddr sdram input clock frequency can be changed under following condition: ddr sdram must be in precharged power down mode with cke at logic low level. after a minimum of 2 clocks after cke goes low, the clock frequency may change to any frequency between minimum and maximum operating frequency specified for the particular speed grade. during an input clock frequency change, cke must be held low. once the input clock frequency is changed, a stable clock must be provided to dram before precharge power down mode may be exited. the dll must be reset via emrs after precharge power down exit. an additional mrs command may need to be issued to appropriately set cl etc. after the dll relock time, the dram is ready to operate with new clock frequency. 7.10 mode register operation the mode register is programmed by the m ode register set command (mrs/emrs) when all banks are in the idle state. the data to be set in the mode register is transferred using the a0 to a11 and ba0, ba1 address inputs. the mode register designates the operation mode for the read or write cycle. the register is divided into five filed: (1) burst length field to set the length of burst data (2) addressing mode selected bit to designate the column access sequence in a burst cycle (3) cas latency field to set the assess time in clock cycle (4) dll reset fi eld to reset the dll (5) regular/extended mode register filed to select a type of mrs (reg ular/extended mrs). emrs cycle can be implemented the extended function (dll enable/disable mode). the initial value of the mode register (including emrs) after power up is undefined; therefore the mode register set command must be issued before power operation. 7.10.1 burst length field (a2 to a0) this field specifies the data length for column acce ss using the a2 to a0 pins and sets the burst length to be 2, 4 and 8 words. a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 x x reserved
W9464G6IB publication release date:oct. 16, 2008 - 15 - revision a01 7.10.2 addressing mode select (a3) the addressing mode can be one of two modes; in terleave mode or sequential mode, when the a3 bit is ?0?, sequential mode is selected. when the a3 bit is ?1?, interleave mode is selected. both addressing mode support burst length 2, 4 and 8 words. a3 addressing mode 0 sequential 1 interleave 7.10.2.1. addressing sequence of sequential mode a column access is performed by incrementing the column address input to the device. the address is varied by the burst length as the following. addressing sequence of sequential mode data access address burst length data 0 n 2 words (address bits is a0) data 1 n + 1 not carried from a0 to a1 data 2 n + 2 4 words (address bit a0, a1) data 3 n + 3 not carried from a1 to a2 data 4 n + 4 data 5 n + 5 8 words (address bits a2, a1 and a0) data 6 n + 6 not carried from a2 to a3 data 7 n + 7 7.10.2.2. addressing sequence for interleave mode a column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. addressing sequence of interleave mode data access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 2 words data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 4 words data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 8 words data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0
W9464G6IB publication release date:oct. 16, 2008 - 16 - revision a01 7.10.3 cas latency field (a6 to a4) this field specifies the number of clock cycles fr om the assertion of the read command to the first data read. the minimum values of cas latency depend on the frequency of clk. a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 2.5 1 1 1 reserved 7.10.4 dll reset bit (a8) this bit is used to reset dll. when the a8 bit is ?1?, dll is reset. 7.10.5 mode register/extended mode register change bits (ba0, ba1) these bits are used to select mrs/emrs. ba1 ba0 a11-a0 0 0 regular mrs cycle 0 1 extended mrs cycle 1 x reserved
W9464G6IB publication release date:oct. 16, 2008 - 17 - revision a01 7.10.6 extended mode register field 1) dll switch field (a0) this bit is used to select dll enable or disable a0 dll 0 enable 1 disable 2) output driver strength control field (a6, a1) the 100%, 60% and 30% or matched impedance driver strength are required extended mode register set (emrs) as the following: a6 a1 buffer strength 0 0 100% strength 0 1 60% strength 1 0 reserved 1 1 30% strength 7.10.7 reserved field ? test mode entry bit (a7) this bit is used to enter test mode and must be set to ?0? for normal operation. ? reserved bits (a9, a10, a11) these bits are reserved for future operations. they must be set to ?0? for normal operation.
W9464G6IB publication release date:oct. 16, 2008 - 18 - revision a01 8. operation mode the following table shows the operation commands. 8.1 simplified truth table sym. command device state cken-1 cken dm (4) ba0, ba1 a10 a0-a9 ,a11 cs ras cas we act bank active idle (3) h x x v v v l l h h pre bank precharge any (3) h x x v l x l l h l prea precharge all any h x x x h x l l h l writ write active (3) h x x v l v l h l l writa write with auto- precharge active (3) h x x v h v l h l l read read active (3) h x x v l v l h l h reada read with auto- precharge active (3) h x x v h v l h l h mrs mode register set idle h x x l, l c c l l l l emrs extended mode register set idle h x x h, l v v l l l l nop no operation any h x x x x x l h h h bst burst read stop active h x x x x x l h h l dsl device deselect any h x x x x x h x x x aref auto refresh idle h h x x x x l l l h self self refresh entry idle h l x x x x l l l h h x x x selex self refresh exit idle (self refresh) l h x x x x l h h x h x x x pd power down mode entry idle/ active (5) h l x x x x l h h x h x x x pdex power down mode exit any (power down) l h x x x x l h h x wde data write enable active h x l x x x x x x x wdd data write disable active h x h x x x x x x x notes : 1. v = valid x = don?t care l = low level h = high level 2. cke n signal is input level when commands are issued. cke n-1 signal is input level one clock cy cle before the commands are issued. 3. these are state designated by the ba0, ba1 signals. 4. ldm, udm (W9464G6IB). 5. power down mode can not entry in the burst cycle.
W9464G6IB publication release date:oct. 16, 2008 - 19 - revision a01 8.2 function truth table (note 1) current state cs ras cas we address command action notes h x x x x dsl nop l h h x x nop/bst nop l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act row activating l l h l ba, a10 pre/prea nop l l l h x aref/self refresh or self refresh 2 idle l l l l op-code mrs/emrs mode register accessing 2 h x x x x dsl nop l h h x x nop/bst nop l h l h ba, ca, a10 read/reada begin read: determine ap 4 l h l l ba, ca, a10 writ/writa begin write: determine ap 4 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea precharge 5 l l l h x aref/self illegal row active l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst burst stop l h l h ba, ca, a10 read/reada term burst, new read: determine ap 6 l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea term burst, precharging l l l h x aref/self illegal read l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, a10 read/reada term burst, start read: determine ap 6, 7 l h l l ba, ca, a10 writ/writa term burst, start read: determine ap 6 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea term burst, precharging 8 l l l h x aref/self illegal write l l l l op-code mrs/emrs illegal
W9464G6IB publication release date:oct. 16, 2008 - 20 - revision a01 function truth table, continued current state cs ras cas we address command action notes h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal l l l h x aref/self illegal read with auto- precharge l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal write with auto- precharge l l l l op-code mrs/emrs illegal h x x x x dsl nop -> idle after t rp l h h h x nop nop -> idle after t rp l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea idle after t rp l l l h x aref/self illegal precharging l l l l op-code mrs/emrs illegal h x x x x dsl nop -> row active after t rcd l h h h x nop nop -> row active after t rcd l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal row activating l l l l op-code mrs/emrs illegal
W9464G6IB publication release date:oct. 16, 2008 - 21 - revision a01 function truth table, continued current state cs ras cas we address command action note s h x x x x dsl nop -> row active after t wr l h h h x nop nop -> row active after t wr l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal write recovering l l l l op-code mrs/emrs illegal h x x x x dsl nop -> enter precharge after t wr l h h h x nop nop -> enter precharge after t wr l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal write recovering with auto- precharge l l l l op-code mrs/emrs illegal h x x x x dsl nop -> idle after t rc l h h h x nop nop -> idle after t rc l h h l x bst illegal l h l h x read/writ illegal l l h x x act/pre/prea illegal refreshing l l l x x aref/self/mrs/emrs illegal h x x x x dsl nop -> row after t mrd l h h h x nop nop -> row after t mrd l h h l x bst illegal l h l x x read/writ illegal mode register accessing l l x x x act/pre/prea/are f/self/mrs/emrs illegal notes : 1. all entries assume that cke was active (high level) during the preceding clock cycle and the current clock cycle. 2. illegal if any bank is not idle. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 4. illegal if t rcd is not satisfied. 5. illegal if t ras is not satisfied. 6. must satisfy burst interrupt condition. 7. must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. must mask preceding data which don?t satisfy t wr remark: h = high level, l = low level, x = high or low level (don?t care), v = valid data
W9464G6IB publication release date:oct. 16, 2008 - 22 - revision a01 8.3 function truth table for cke cke current state n-1 n cs ras cas we address action notes h x x x x x x invalid l h h x x x x exit self refresh -> idle after t xsnr l h l h h x x exit self refresh -> idle after t xsnr l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x maintain self refresh h x x x x x x invalid l h x x x x x exit power down -> idle after t is power down l l x x x x x maintain power down mode h h x x x x x refer to function truth table h l h x x x x enter power down 2 h l l h h x x enter power down 2 h l l l l h x self refresh 1 h l l h l x x illegal h l l l x x x illegal all banks idle l x x x x x x power down h h x x x x x refer to function truth table h l h x x x x enter power down 3 h l l h h x x enter power down 3 h l l l l h x illegal h l l h l x x illegal h l l l x x x illegal row active l x x x x x x power down any state other than listed above h h x x x x x refer to function truth table notes : 1. self refresh can enter only from the all banks idle state. 2. power down occurs when all banks are idle; this mode is referred to as precharge power down. 3. power down occurs when there is a row active in an y bank; this mode is referred to as active power down. remark: h = high level, l = low level, x = high or low level (don?t care), v = valid data
W9464G6IB publication release date:oct. 16, 2008 - 23 - revision a01 8.4 simplified stated diagram power applied automatic sequence command sequence read a write read row active power down idle mode register set auto refresh self refresh read read a write write a pre charge power on mrs/emrs aref sref srefx pd pdex act bst read write write a write a read a pre pre pre pre active powerdown pd pdex read read a
W9464G6IB publication release date:oct. 16, 2008 - 24 - revision a01 9. electrical characteristics 9.1 absolute maximum ratings parameter symbol rating unit voltage on i/o pins relative to v ss v in, v out -0.5 ~ v ddq +0.5 v voltage on input pins relative to v ss v in -1 ~ 3.6 v voltage on v dd supply relative to v ss v dd -1 ~ 3.6 v voltage on v ddq supply relative to v ss v ddq -1 ~ 3.6 v operating temperature t opr 0 ~ 70 c storage temperature t stg -55 ~ 150 c soldering temperature (10s) t solder 260 c power dissipation p d 1 w short circuit output current i out 50 ma note: stresses greater than those listed under ?absolute maxi mum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the dev ice at these or any other conditions above those indicate d in the operational sections of this specification is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect reliability. 9.2 recommended dc operating conditions (t a = 0 to 70 c) symbol parameter min. typ. max. unit notes v dd power supply voltage 2.3 2.5 2.7 v 2 v ddq power supply voltage (for i/o buffer) 2.3 2.5 2.7 v 2 v ref input reference voltage 0.49 x v ddq 0.50 x v ddq 0.51 x v ddq v 2, 3 v tt termination voltage (system) v ref - 0.04 vref v ref + 0.04 v 2, 8 v ih (dc) input high voltage (dc) v ref + 0.15 - v ddq + 0.3 v 2 v il (dc) input low voltage (dc) -0.3 - v ref - 0.15 v 2 v ick (dc) differential clock dc input voltage -0.3 - v ddq + 0.3 v 15 v id (dc) input differential voltage. clk and clk inputs (dc) 0.36 - v ddq + 0.6 v 13, 15 v ih (ac) input high voltage (ac) v ref + 0.31 - - v 2 v il (ac) input low voltage (ac) - - v ref - 0.31 v 2 v id (ac) input differential voltage. clk and clk inputs (ac) 0.7 - v ddq + 0.6 v 13, 15 v x (ac) differential ac input cross point voltage v ddq /2 - 0.2 - v ddq /2 + 0.2 v 12, 15 v iso (ac) differential clock ac middle point v ddq /2 - 0.2 - v ddq /2 + 0.2 v 14, 15 notes : undershoot limit: v il (min) = -1.5v with a pulse width < 5 ns overshoot limit: v ih (max) = v ddq +1.5v with a pulse width < 5 ns v ih (dc) and v il (dc) are levels to maintain the current logic state. v ih (ac) and v il (ac) are levels to change to the new logic state.
W9464G6IB publication release date:oct. 16, 2008 - 25 - revision a01 9.3 capacitance (v dd = v ddq = 2.5v 0.2v, f = 1 mhz, t a = 25 c, v out (dc) = v ddq /2, v out (peak to peak) = 0.2v) symbol parameter min. max. delta (max.) unit c in input capacitance (except for clk pins) 1.5 2.5 0.5 pf c clk input capacitance (clk pins) 1.5 2.5 0.25 pf c i/o dq, dqs, dm capacit ance 3.5 4.5 0.5 pf notes: these parameters are periodically sampled and not 100% tested. 9.4 leakage and output buffer characteristics symbol parameter min. max. unit notes i i (l) input leakage current any input 0v < v in < v dd , v ref pin 0v < v in < 1.35v (all other pins not under test = 0v) -2 2 a i o (l) output leakage current (output disabled, 0v < v out < v ddq ) -5 5 a v oh output high voltage (under ac test load condition) v tt +0.76 - v v ol output low voltage (under ac test load condition) - v tt -0.76 v i oh output levels: full drive option high current (v out = v ddq - 0.373v, min. v ref , min. v tt -15 - ma 4, 6 i ol low current (v out = 0.373v, max. v ref , max. v tt ) 15 - ma 4, 6 i ohr output levels: reduced drive option - 60% high current (v out = v ddq - 0.763v, min. v ref , min. v tt -9 - ma 5 i olr low current (v out = 0.763v, max. vref, max. v tt ) 9 - ma 5 i ohr (30) output levels: reduced drive option - 30% high current (v out = v ddq ? 1.056v, min. v ref , min. v tt -4.5 - ma 5 i olr (30) low current (v out = 1.056v, max. v ref , max. v tt ) 4.5 - ma 5
W9464G6IB publication release date:oct. 16, 2008 - 26 - revision a01 9.5 dc characteristics max. sym. parameter -5 unit notes i dd0 operating current: one b ank active-precharge; t rc = t rc min; t ck = t ck min; dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 120 7 i dd1 operating current: one bank active-read-precharge; burst = 4; t rc = t rc min; cl = 3; t ck = t ck min; i out = 0 ma; address and control inputs changing once per clock cycle 140 7, 9 i dd2p precharge power down standby current: all banks idle; power down mode; cke < v il max; t ck = t ck min; vin = v ref for dq, dqs and dm 20 i dd2n idle standby current: cs > v ih min; all banks idle; cke > v ih min; t ck = t ck min; address and other control inputs changing once per clock cycle; vin > v ih min or vin < v il max for dq, dqs and dm 50 i dd2f idle floating standby current: cs > v ih min; all banks idle; cke > v ih min; address and other control inputs changing once per clock cycle; vin = v ref for dq, dqs and dm 50 7 i dd2q idle quiet standby current: cs > v ih min; all banks idle; cke > v ih min; t ck = t ck min; address and other control inputs stable; vin = v ref for dq, dqs and dm 50 7 i dd3p active power down standby current: one bank active; power down mode; cke < v il max; t ck = t ck min; vin = v ref for dq, dqs and dm 30 i dd3n active standby current: cs > v ih min; cke > v ih min; one bank active-precharge; t rc = t ras max; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and other control input s changing once per clock cycle 60 7 i dd4r operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl=2; t ck = t ck min; i out = 0ma 185 7, 9 i dd4w operating current: burst = 2; write; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl = 2; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle 180 7 i dd5 auto refresh current: t rc = t rfc min 210 7 i dd6 self refresh current: cke < 0.2v; external clock on; t ck = t ck min 2.5 i dd7 random read current: 4 banks active read with activate every 20ns, auto-precharge read every 20 ns; burst = 4; t rcd = 3; i out = 0ma; dq, dm and dqs inputs changing twice per clock cycle; address changing once per clock cycle 320 ma
W9464G6IB publication release date:oct. 16, 2008 - 27 - revision a01 9.6 ac characteristics and operating condition (notes: 10, 12) -5 sym. parameter min. max. unit notes t rc active to ref/active command period 55 t rfc ref to ref/active command period 70 t ras active to precharge command period 40 70000 t rcd active to read/write command delay time 15 t rap active to read with auto-precharge enable 15 ns t ccd read/write(a) to read/write(b) command period 1 t ck t rp precharge to active command period 15 t rrd active(a) to active(b) command period 10 t wr write recovery time 15 ns t dal auto-precharge write recovery + precharge time -- t ck 18 cl = 2 7.5 10 cl = 2.5 6 10 t ck clk cycle time cl = 3 5 10 t ac data access time from clk, clk -0.7 0.7 16 t dqsck dqs output access time from clk, clk -0.6 0.6 16 t dqsq data strobe edge to output data edge skew 0.4 ns t ch clk high level width 0.45 0.55 11 t cl clk low level width 0.45 0.55 t ck 11 t hp clk half period (minimum of actual t ch, t cl ) min. (t cl ,t ch ) t qh dq output data hold time from dqs t hp -0.5 ns t rpre dqs read preamble time 0.9 1.1 11 t rpst dqs read postamble time 0.4 0.6 t ck 11 t ds dq and dm setup time 0.4 t dh dq and dm hold time 0.4 t dipw dq and dm input pulse width (for each input) 1.75 ns t dqsh dqs input high pulse width 0.35 11 t dqsl dqs input low pulse width 0.35 11 t dss dqs falling edge to clk setup time 0.2 11 t dsh dqs falling edge hold time from clk 0.2 t ck 11 t wpres clock to dqs write preamble set-up time 0 ns t wpre dqs write preamble time 0.25 11 t wpst dqs write postamble time 0.4 0.6 11 t dqss write command to first dqs latching transition 0.72 1.25 t ck 11 t is input setup time (fast slew rate) 0.6 19, 21-23 t ih input hold time (fast slew rate) 0.7 19, 21-23 t is input setup time (slow slew rate) 0.6 20-23 t ih input hold time (slow slew rate) 0.7 20-23 t ipw control & address input pulse width (for each input) 2.2 t hz data-out high-impedance time from clk, clk 0.7 t lz data-out low-impedance time from clk, clk -0.7 0.7 t t(ss) sstl input transition 0.5 1.5 ns t wtr internal write to read command delay 2 t ck t xsnr exit self refresh to non-read command 75 ns t xsrd exit self refresh to read command 200 t ck t refi refresh time (4k/64ms) 15.6 s 17 t mrd mode register set cycle time 10 ns
W9464G6IB publication release date:oct. 16, 2008 - 28 - revision a01 9.7 ac test conditions parameter symbol value unit input high voltage (ac) v ih v ref + 0.31 v input low voltage (ac) v il v ref - 0.31 v input reference voltage v ref 0.5 x v ddq v termination voltage v tt 0.5 x v ddq v differential clock input reference voltage v r v x (ac) v input difference voltage. clk and clk inputs (ac) v id (ac) 1.5 v output timing measurement reference voltage v otr 0.5 x v ddq v v swing (max) v dd q v ss t t v ih min (ac) v ref v il max (ac) slew = (v ih min (ac) - v il max (ac)) / t output notes: (1) conditions outside the limits listed under ?absolute maximum ratings? may cause permanent damage to the device. (2) all voltages are referenced to v dd , v ddq. (3) peak to peak ac noise on v ref may not exceed 2% v ref(dc). (4) v oh = 1.95v, v ol = 0.35v (5) v oh = 1.9v, v ol = 0.4v (6) the values of i oh(dc) is based on v ddq = 2.3v and v tt = 1.19v. the values of i ol(dc) is based on v ddq = 2.3v and v tt = 1.11v. (7) these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck and t rc . (8) v tt is not applied directly to the device. v tt is a system supply for signal terminat ion resistors is expected to be set equal to v ref and must track variations in the dc level of v ref . (9) these parameters depend on the output loading. spec ified values are obtained with the output open. (10) transition times are measured between v ih min(ac) and v il max(ac) .transition (rise and fall) of input signals have a fixed slope. (11) if the result of nominal calculation with regard to t ck contains more than one decimal pl ace, the result is rounded up to the nearest decimal place. (i.e., t dqss = 0.75 t ck , t ck = 7.5 ns, 0.75 7.5 ns = 5.625 ns is rounded up to 5.6 ns.)
W9464G6IB publication release date:oct. 16, 2008 - 29 - revision a01 (12) v x is the differential clock cross point volt age where input timing meas urement is referenced. (13) v id is magnitude of the difference between clk input level and clk input level. (14) v iso means {v ick (clk)+v ick ( clk )}/2. (15) refer to the figure below. clk clk v ss v ick v x v x v x v x v x v ick v ick v ick v id(ac) v id(ac) 0 v differential v iso v iso(min) v iso(max) v ss (16) t ac and t dqsck depend on the clock jitter. these timi ng are measured at stable clock. (17) a maximum of eight auto refresh commands can be posted to any gi ven ddr sdram device. (18) t dal = (t wr /t ck ) + (t rp /t ck ) (19) for command/address input slew rate 1.0 v/ns. (20) for command/address input slew rate 0.5 v/ns and <1.0 v/ns. (21) for clk & clk slew rate 1.0 v/ns (single--ended). (22) these parameters guarantee device timing, but they ar e not necessarily tested on each device. they may be guaranteed by device design or tester correlation. (23) slew rate is measured between voh(ac) and vol(ac).
W9464G6IB publication release date:oct. 16, 2008 - 30 - revision a01 10. system characteristics for ddr sdram the following specification parameters are requi red in systems using ddr400 devices to ensure proper system performance. these characterist ics are for system simulation purposes and are guaranteed by design. 10.1 table 1: input slew rate for dq, dqs, and dm ac characteristics ddr400 parameter symbol min. max. unit notes dq/dm/dqs input slew rate measured between v ih(dc) , v il(dc) and v il(dc) , v ih(dc) dcslew 0.5 4.0 v/ns a, k 10.2 table 2: input setup & hold time derating for slew rate input slew rate t is t ih unit notes 0.5 v/ns 0 0 ps h 0.4 v/ns +50 0 ps h 0.3 v/ns +100 0 ps h 10.3 table 3: input/output setup & hold time derating for slew rate input slew rate t ds t dh unit notes 0.5 v/ns 0 0 ps j 0.4 v/ns +75 0 ps j 0.3 v/ns +150 0 ps j 10.4 table 4: input/output setup & hold derating for rise/fall delta slew rate input slew rate t ds t dh unit notes r 0.0 ns/v 0 0 ps i r 0.25 ns/v +50 0 ps i r 0.5 ns/v +100 0 ps i 10.5 table 5: output slew rate characteristics (x16 devices only) slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0. 7 5.0 a, c, d, e, f, g pulldown slew rate 1.2 ~ 2.5 0.7 5.0 a, c, d, e, f, g
W9464G6IB publication release date:oct. 16, 2008 - 31 - revision a01 10.6 system notes: a. pullup slew rate is characterized under the test conditions as shown in figure 1. vssq 50 output test point figure 1: pullup slew rate test load b. pulldown slew rate is measured under the test conditions shown in figure 2. figure 2: pulldown slew rate test load c. pullup slew rate is measured between (v ddq /2 - 320 mv 250 mv) pulldown slew rate is measured between (v ddq /2 + 320 mv 250 mv) pullup and pulldown slew rate conditions are to be me t for any pattern of data, including all outputs switching and only one output switching. example: for typical slew rate, dq0 is switching for minimum slew rate, all dq bits are switching worst case pattern for maximum slew rate, only one dq is switchin g from either high to low, or low to high the remaining dq bits remain the same as for previous state d. evaluation conditions typical: 25 o c (t ambient), v ddq = nominal, typical process minimum: 70 o c (t ambient), v ddq = minimum, sl ow-slow process maximum: 0 o c (t ambient), v ddq = maximum, fast-fast process e. verified under typical conditions for qualification purposes. f. tsop ii package devices only. g. only intended for operation up to 266 mbps per pin.
W9464G6IB publication release date:oct. 16, 2008 - 32 - revision a01 h. a derating factor will be used to increase t is and t ih in the case where the input slew rate is below 0.5 v/ns as shown in table 2. the input slew ra te is based on the lesser of the slew rates determined by either v ih(ac) to v il(ac) or v ih(dc) to v il(dc) , similarly for rising transitions. i. a derating factor w ill be used to increase t ds and t dh in the case where dq, dm, and dqs slew rates differ, as shown in tables 3 & 4. input slew rate is based on the larger of ac-ac delta rise, fall rate and dc-dc delta rise, fall rate. input slew rate is based on the lesser of the slew rates determined by either v ih(ac) to v il(ac) or v ih(dc) to v il(dc) , similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)}-{1/(slew rate2)} for example: if slew rate 1 is 0.5 v/ns and slew ra te 2 is 0.4 v/ns, then the delta rise, fall rate is -0.5 ns/v. using the table given, this woul d result in the need for an increase in t ds and t dh of 100 ps. j. table 3 is used to increase t ds and t dh in the case where the i/o slew rate is below 0.5 v/ns. the i/o slew rate is based on the lesser of the ac-a c slew rate and the dc-dc slew rate. the input slew rate is based on the lesser of the slew rates determined by either v ih(ac) to v il(ac) or v ih(dc) to v il(dc) , and similarly for rising transitions. k. dqs, dm, and dq input slew rate is specifi ed to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic.
W9464G6IB publication release date:oct. 16, 2008 - 33 - revision a01 11. timing waveforms 11.1 command input timing clk clk t ck t ck t cl t ch t is t ih t is t ih t is t ih t is t ih t is t ih cs ras cas we a0~a11 ba0,1 refer to the command truth table 11.2 timing of the clk signals t ck t t t t v ih v ih(ac) v il(ac) v il clk clk clk clk v x v x v x v ih v il t ch t cl
W9464G6IB publication release date:oct. 16, 2008 - 34 - revision a01 11.3 read timing (burst length = 4) t is t ih da0 da1 da2 t ch t cl t ck add cmd clk clk read col qa0 qa1 qa2 da3 qa3 t rpre t dqsck t dqsck t dqsck t rpst postamble preamble hi-z hi-z t dqsq t dqsq t dqsq t qh t qh t ac t lz t hz hi-z hi-z da0 da1 da2 qa0 qa1 qa2 da3 qa3 t rpre t dqsck t dqsck t dqsck t rpst postamble preamble hi-z hi-z t dqsq t dqsq t dqsq t qh t qh t ac t lz t hz hi-z hi-z cas latency = 2 dqs output (data) cas latency = 3 dqs output (data) t is t ih notes : the correspondence of ldqs, udqs to dq. (W9464G6IB) ldqs dq0~7 udqs dq8~15
W9464G6IB publication release date:oct. 16, 2008 - 35 - revision a01 11.4 write timing (burst length = 4) t is t ih tdsh t dss t dss t dsh t wpres t dh t dh t dh t ds t ds t ds t dqss t dsh t dsh t dss t dss postamble t wpre preamble t dqsh t dqsh t dqsl t wpst da0 da1 da2 da3 t wpres t ds t ds t dqss t dsh t dsh t dss t dss postamble t wpre preamble t dqsh t dqsh t dqsl t wpst t wpres t dh t ds t ds t dqss postamble t wpre preamble t dqsh t dqsh t dqsl t wpst da0 da1 da2 da3 t ds t dh t dh t ch t cl t ck dqs input (data) ldqs dq0~7 udqs dq8~15 x4, x8 device x16 device add cmd clk clk writ col da0 da1 da2 da3 da0 da1 da2 da3 t dh t dh t dh t ds da0 da1 da2 da3 da0 da1 da2 da3 t is t ih note: x16 has two dqss (udqs for upper byte and ldqs for lower byte). even if one of the 2 bytes is not used, both udqs and ldqs must be toggled.
W9464G6IB publication release date:oct. 16, 2008 - 36 - revision a01 11.5 dm, data mask (W9464G6IB) writ t dipw t dipw t dh t dh t ds t ds masked clk cmd ldqs ldm dq0~dq7 d3 d1 d0 t dipw t dipw t dh t dh t ds t ds m asked udqs udm dq8~dq15 d3 d2 d0 clk
W9464G6IB publication release date:oct. 16, 2008 - 37 - revision a01 11.6 mode register set (mrs) timing mrs register set data next cmd t mrd clk clk cmd add a2 a1 a0 a3 a6 a5 a4 a8 ba1 ba0 000 000 001 010 011 100 101 110 111 001 010 011 100 101 110 111 0 1 0 1 1 1 0 0 0 1 0 1 2 4 8 2 4 8 burst length sequential interleaved reserved reserved reserved reserved reserved reserved sequential interleaved addressing mode cas latency 2 dll reset no yes mrs or emrs regular mrs cycle extended mrs cycle 2.5 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ba0 ba1 "0" "0" "0" "0" "0" "0" dll reset reserved addressing mode * "reserved" should stay "0" during mrs cycle. reserved mode register set or extended mode register set cas latency burst length reserved reserved 3
W9464G6IB publication release date:oct. 16, 2008 - 38 - revision a01 11.7 extend mode register set (emrs) timing emrs register set data next cmd t mrd clk clk cmd add a0 ba1 ba0 0 1 1 1 0 0 0 1 0 1 enable disable dll switch mrs or emrs regular mrs cycle extended mrs cycle a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ba0 ba1 "0" "0" "0" "0" "0" "0" * "reserved" should stay "0" during emrs cycle. "0" "0" "0" "0" "0" "0" buffer strength dll switch reserved mode register set or extended mode register set reserved buffer strength a1 buffer strength 100% strength a6 1 1 0 0 0 1 0 1 60% strength 30% strength reserved
W9464G6IB publication release date:oct. 16, 2008 - 39 - revision a01 11.8 auto-precharge timing (read cycle, cl = 2) 1. t rcd (reada) t ras (min) ? (bl/2) t ck ap q7 q6 q5 q4 q3 q2 q1 q0 act reada act q0 q1 q2 q3 act reada act q0 q1 act ap reada act trp t ras cmd dqs dq cmd dqs dq cmd dqs dq bl=2 bl=4 bl=8 clk clk ap notes: cl=2 shown; same command operation timing with cl = 2,5 and cl=3 in this case, the internal precharge operation begin after bl/2 cycle from reada command. ap represents the start of internal precharging. the read with auto-precharge command cannot be interrupted by any other command.
W9464G6IB publication release date:oct. 16, 2008 - 40 - revision a01 11.9 auto-precharge timing (read cycle, cl = 2), continued 2. t rcd/rap(min) t rcd (reada) < t ras (min) ? (bl/2) t ck ap q7 q6 q5 q4 q3 q2 q1 q0 act reada act q0 q1 q2 q3 act reada act q0 q1 act ap reada act t rp t ras cmd dqs dq cmd dqs dq cmd dqs dq bl=2 bl=4 bl=8 clk clk ap t rap t rcd t rap t rcd t rap t rcd notes: cl2 shown; same command operation timing with cl = 2.5, cl=3. in this case, the internal precharge operation does not begin until after t ras (min) has command. ap represents the start of internal precharging. the read with auto-precharge command cannot be interrupted by any other command.
W9464G6IB publication release date:oct. 16, 2008 - 41 - revision a01 11.10 auto-precharge timing (write cycle) ap writa act act writa act writa cmd dqs dq cmd dqs dq cmd dqs dq bl=2 bl=4 bl=8 clk clk ap ap d0 d1 d0 d1 d2 d3 d0 d1 d2 d3 d4 d5 d6 d7 t dal t dal t dal the write with auto-precharge command cannot be interrupted by any other command. ap represents the start of internal precharging.
W9464G6IB publication release date:oct. 16, 2008 - 42 - revision a01 11.11 read interrupted by read (cl = 2, bl = 2, 4, 8) cmd add dqs clk clk dq act read a read b read c read d read e row address col,add,a col,add,b col,add,c col,add,d col,add,e qc0 qa0 qa1 qb0 qb1 t ccd t ccd t ccd t ccd t rcd 11.12 burst read stop (bl = 8) read cmd dqs dq clk clk bst q0 q1 q2 q3 q4 q5 q0 q1 q2 q3 q4 q5 cas latency cas latency cas latency = 2 dqs dq cas latency = 3
W9464G6IB publication release date:oct. 16, 2008 - 43 - revision a01 11.13 read interrupted by write & bst (bl = 8) read cmd dqs dq clk clk bst q0 q1 q2 q3 q4 q5 cas latency = 2 writ d0 d1 d2 d3 d4 d5 d6 d7 burst read cycle must be terminated by bst command to avoid i/o conflict. 11.14 read interrupted by precharge (bl = 8) read cmd dqs dq clk clk pre q0 q1 q2 q3 q4 q5 q0 q1 q2 q3 q4 q5 cas latency cas latency cas latency = 2 dqs dq cas latency = 3
W9464G6IB publication release date:oct. 16, 2008 - 44 - revision a01 11.15 write interrupted by write (bl = 2, 4, 8) cmd add dqs clk clk dq act writ a writ b writ c writ d writ e row address col. add. a col.add.b col. add. c col. add. d col. add. e dc0 dc1 dd0 dd1 da0 da1 db0 db1 t ccd t ccd t ccd t ccd t rcd 11.16 write interrupted by read (cl = 2, bl = 8) writ cmd dqs dm clk clk t wtr dq d4 d5 d6 d7 d0 d1 d2 d3 data must be masked by dm read data masked by read command, dqs input ignored. q4 q5 q6 q7 q0 q1 q2 q3
W9464G6IB publication release date:oct. 16, 2008 - 45 - revision a01 11.17 write interrupted by read (cl = 3, bl = 4) writ cmd dqs dm clk clk read t wtr dq q0 q1 q2 q3 d0 d1 d2 d3 data must be masked by dm 11.18 write interrupted by precharge (bl = 8) writ cmd dqs dm clk clk act t wr dq d4 d5 d6 d7 d0 d1 d2 d3 data must be masked by dm pre t rp data masked by pre command, dqs input ignored.
W9464G6IB publication release date:oct. 16, 2008 - 46 - revision a01 11.19 2 bank interleave read operation (cl = 2, bl = 2) ? t ck = 100 mhz cmd dqs clk clk dq q0a q1a q0b q1b acta/b : bank act. cmd of bank a/b readaa/b : read with auto pre.cmd of bank a/b apa/b : auto pre. of bank a/b acta actb readaa acta readab actb apa apb t rcd(a) t ras(a) t rp(a) t ras(b) t rcd(b) t rp(b) cl(a) cl(b) preamble postamble preamble postamble t rrd t rc(a) t rc(b) t rrd 11.20 2 bank interleave read operation (cl = 2, bl = 4) cmd dqs clk clk dq q2a q3a q2b q3b acta/b : bank act. cmd of bank a/b readaa/b : read with auto pre.cmd of bank a/b apa/b : auto pre. of bank a/b acta readaa actb readab acta actb apa apb t rcd(a) t ras(a) t rp(a) t ras(b) t rcd(b) t rp(b) cl(a) cl(b) preamble postamble t rrd t rc(a) t rc(b) t rrd q0a q1a q0b q1b
W9464G6IB publication release date:oct. 16, 2008 - 47 - revision a01 11.21 4 bank interleave read operation (cl = 2, bl = 2) cmd dqs clk clk dq q0a q1a q0b q1b acta/b/c/d : bank act. cmd of bank a/b/c/d readaa/b/c/d : read with auto pre.cmd of bank a/b/c/d apa/b/c/d : auto pre. of bank a/b/c/d acta actb readaa actc readab actd readac acta apa apb t rcd(a) t ras(a) t rp t ras(b) t rcd(b) cl(a) cl(b) preamble postamble preamble t rrd t rc(a) t rrd t ras(c) t ras(d) t rcd(d) t rcd(c) t rrd t rrd 11.22 4 bank interleave read operation (cl = 2, bl = 4) cmd dqs clk clk dq acta/b/c/d : bank act. cmd of bank a/b/c/d readaa/b/c/d : read with auto pre.cmd of bank a/b/c/d apa/b/c/d : auto pre. of bank a/b/c/d acta readaa actb readab actc readac actd readad acta apa apb t rcd(a) t ras(a) t rp(a) t ras(b) t rcd(b) cl(a) cl(b) t rrd t rc(a) t rrd t ras(c) t ras(d) t rcd(d) t rcd(c) t rrd t rrd q2a q3a q2b q3b preamble q0a q1a q0b q1b q0a q1a cl(c) apc
W9464G6IB publication release date:oct. 16, 2008 - 48 - revision a01 11.23 auto refresh cycle cmd clk clk prea aref aref cmd nop nop nop t rp t rfc t rfc note: cke has to be kept ?high? level for auto-refresh cycle. 11.24 precharge/activate power down mode entry and exit timing cmd clk clk nop cmd nop exit entry cmd nop t ih t is t ck t ih t is cke precharge/activate note 1,2 note: 1. if power down occurs when all banks are idle, this mode is referred to as precharge power down. 2. if power down occurs when there is a row active in an y bank, this mode is referred to as active power down. 11.25 input clock frequency change during precharge power down mode timing nop nop nop dll reset nop nop cmd 200 clocks t is frequency change occurs here minmum 2 clocks required before changing frequency stable new clock before power down exit clk clk cmd cke t rp
W9464G6IB publication release date:oct. 16, 2008 - 49 - revision a01 11.26 self refresh entry and exit timing cmd clk clk t ih t is t ih t is self cmd selex nop nop prea exit entry cke t rp t xsrd nop self t xsnr selfx nop act read nop exit entry note: if the clock frequency is changed during self refres h mode, a dll reset is required upon exit.
W9464G6IB publication release date:oct. 16, 2008 - 50 - revision a01 12. package specification 12.1 60 ball tfbga (8x13mm) a b a1 a s s 0.1 s 0.2 // solder ball 60x b symbol a a1 b d e1 e e1 e2 d1 f dimension in inch dimension in mm min nom max min nom max --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.01 0.016 0.507 0.003 0.039 0.031 0.252 0.315 0.433 0.512 0.051 0.016 0.02 0.515 0.318 7.9 0.1 12.9 0.40 0.25 13.0 11.0 8.0 6.40 0.80 1.00 8.1 13.1 0.50 0.40 1.20 a d d1 e1 e1 e e2 0.50 c 0.20 package type: 60 ball csp m b 0.15 a 0.08 s s detail a f note: solder ball is 0.45mm before reflow sb 0.20 a s m 0.20 c 0.10 c c 0.1 // m m 0.311
W9464G6IB publication release date:oct. 16, 2008 - 51 - revision a01 13. revision history version date page description a01 oct. 16, 2008 all formally data sheet important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surg ical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.


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